The scaling of CMOS technology leads to a greater difficulty in the integration of both floating gate memory and logic together for high performance and low power system-on-chip (SoC). Floating gate memory can provide embedded multi-time programmable memory (MTP), Electrically Erasable Programmable Read-Only Memory (EEPROM) and Flash memory and is typically 2 or 3 nodes behind leading edge CMOS technology, because of the complexity of integrating additional processing (which also increases the costs). As a result, one-time programmable (OTP) memory is being used increasingly for embedded non-volatile memory (NVM) applications.
In an OTP memory it is impossible to exercise the memory during testing to identify any defective cells. Conventionally the OTP memory is programmed at chip test and so the final programmed device can be tested before the device is shipped to a customer and devices which have not been programmed correctly can be screened out. However, where such cells are programmed during the operation of the device, this is not possible, and this is exacerbated where large numbers of OTP cells are used in this manner.
The embodiments described below are not limited to implementations which solve any or all of the disadvantages of known OTP elements and associated control circuitry.